Synthesis Report #Build: Synplify Pro (R) Q-2020.03L-SP1, Build 182R, Oct 29 2020 #install: C:\lscc\diamond\3.12\synpbase #OS: Windows 8 6.2 #Hostname: DESKTOP-5F8QMCQ # Thu Apr 3 13:14:27 2025 #Implementation: impl1 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: DESKTOP-5F8QMCQ Implementation : impl1 Synopsys HDL Compiler, Version comp202003synp2, Build 182R, Built Oct 29 2020 10:49:53, @ @N|Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: DESKTOP-5F8QMCQ Implementation : impl1 Synopsys Verilog Compiler, Version comp202003synp2, Build 182R, Built Oct 29 2020 10:49:53, @ @N|Running in 64-bit mode @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work) @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\Users\lab\Desktop\TOP.v" (library work) Verilog syntax check successful! Options changed - recompiling Selecting top level module bin_to_bcd @N: CG364 :"C:\Users\lab\Desktop\TOP.v":1:7:1:15|Synthesizing module bcd_shl_1 in library work. Running optimization stage 1 on bcd_shl_1 ....... @N: CG364 :"C:\Users\lab\Desktop\TOP.v":29:7:29:16|Synthesizing module bin_to_bcd in library work. Running optimization stage 1 on bin_to_bcd ....... Running optimization stage 2 on bin_to_bcd ....... Running optimization stage 2 on bcd_shl_1 ....... @N: CL201 :"C:\Users\lab\Desktop\TOP.v":9:0:9:5|Trying to extract state machine for register DAT. Extracted state machine for register DAT State machine has 10 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 For a summary of runtime and memory usage per design unit, please see file: ========================================================== @L: C:\Users\lab\Desktop\impl1\synwork\layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 92MB peak: 92MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Apr 3 13:14:28 2025 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: DESKTOP-5F8QMCQ Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 182R, Built Oct 29 2020 10:49:53, @ @N|Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 90MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Apr 3 13:14:29 2025 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== @L: C:\Users\lab\Desktop\impl1\synwork\bcd_test_impl1_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 29MB peak: 29MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Apr 3 13:14:29 2025 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: DESKTOP-5F8QMCQ Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 182R, Built Oct 29 2020 10:49:53, @ @N|Running in 64-bit mode File C:\Users\lab\Desktop\impl1\synwork\bcd_test_impl1_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Apr 3 13:14:30 2025 ###########################################################] Premap Report # Thu Apr 3 13:14:30 2025 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: DESKTOP-5F8QMCQ Implementation : impl1 Synopsys Lattice Technology Pre-mapping, Version map202003lat, Build 172R, Built Nov 2 2020 09:31:45, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @A: MF827 |No constraint file specified. @L: C:\Users\lab\Desktop\impl1\bcd_test_impl1_scck.rpt See clock summary report "C:\Users\lab\Desktop\impl1\bcd_test_impl1_scck.rpt" @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 128MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 128MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 155MB peak: 155MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 165MB peak: 167MB) Encoding state machine DAT_1[9:0] (in view: work.bcd_shl_1_9(verilog)) original code -> new code 0000 -> 0000 0001 -> 0001 0010 -> 0010 0011 -> 0011 0100 -> 0100 0101 -> 0101 0110 -> 0110 0111 -> 0111 1000 -> 1000 1001 -> 1001 Encoding state machine DAT_1[9:0] (in view: work.bcd_shl_1_8(verilog)) original code -> new code 0000 -> 0000 0001 -> 0001 0010 -> 0010 0011 -> 0011 0100 -> 0100 0101 -> 0101 0110 -> 0110 0111 -> 0111 1000 -> 1000 1001 -> 1001 Encoding state machine DAT_1[9:0] (in view: work.bcd_shl_1_7(verilog)) original code -> new code 0000 -> 0000 0001 -> 0001 0010 -> 0010 0011 -> 0011 0100 -> 0100 0101 -> 0101 0110 -> 0110 0111 -> 0111 1000 -> 1000 1001 -> 1001 Encoding state machine DAT_1[9:0] (in view: work.bcd_shl_1_6(verilog)) original code -> new code 0000 -> 0000 0001 -> 0001 0010 -> 0010 0011 -> 0011 0100 -> 0100 0101 -> 0101 0110 -> 0110 0111 -> 0111 1000 -> 1000 1001 -> 1001 Encoding state machine DAT_1[9:0] (in view: work.bcd_shl_1_5(verilog)) original code -> new code 0000 -> 0000 0001 -> 0001 0010 -> 0010 0011 -> 0011 0100 -> 0100 0101 -> 0101 0110 -> 0110 0111 -> 0111 1000 -> 1000 1001 -> 1001 Encoding state machine DAT_1[9:0] (in view: work.bcd_shl_1_4(verilog)) original code -> new code 0000 -> 0000 0001 -> 0001 0010 -> 0010 0011 -> 0011 0100 -> 0100 0101 -> 0101 0110 -> 0110 0111 -> 0111 1000 -> 1000 1001 -> 1001 Encoding state machine DAT_1[9:0] (in view: work.bcd_shl_1_3(verilog)) original code -> new code 0000 -> 0000 0001 -> 0001 0010 -> 0010 0011 -> 0011 0100 -> 0100 0101 -> 0101 0110 -> 0110 0111 -> 0111 1000 -> 1000 1001 -> 1001 Encoding state machine DAT_1[9:0] (in view: work.bcd_shl_1_2(verilog)) original code -> new code 0000 -> 0000 0001 -> 0001 0010 -> 0010 0011 -> 0011 0100 -> 0100 0101 -> 0101 0110 -> 0110 0111 -> 0111 1000 -> 1000 1001 -> 1001 Encoding state machine DAT_1[9:0] (in view: work.bcd_shl_1_1(verilog)) original code -> new code 0000 -> 0000 0001 -> 0001 0010 -> 0010 0011 -> 0011 0100 -> 0100 0101 -> 0101 0110 -> 0110 0111 -> 0111 1000 -> 1000 1001 -> 1001 Encoding state machine DAT_1[9:0] (in view: work.bcd_shl_1_0(verilog)) original code -> new code 0000 -> 0000 0001 -> 0001 0010 -> 0010 0011 -> 0011 0100 -> 0100 0101 -> 0101 0110 -> 0110 0111 -> 0111 1000 -> 1000 1001 -> 1001 Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB) Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 196MB) @N: FX1184 |Applying syn_allowed_resources blockrams=10 on top level netlist bin_to_bcd Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 196MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load --------------------------------------------------------------------------------------------------- 0 - bin_to_bcd|CLK 200.0 MHz 5.000 inferred Inferred_clkgroup_0 147 =================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ------------------------------------------------------------------------------------------ bin_to_bcd|CLK 147 CLK(port) O_STB.C - - ========================================================================================== @W: MT529 :"c:\users\lab\desktop\top.v":9:0:9:5|Found inferred clock bin_to_bcd|CLK which controls 147 sequential elements including b0.DAT_1[3]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 147 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- @KP:ckid0_0 CLK port 147 O_DAT[39:0] ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ###### @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 196MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 197MB) Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 197MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 116MB peak: 198MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Apr 3 13:14:32 2025 ###########################################################] Map & Optimize Report # Thu Apr 3 13:14:32 2025 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: DESKTOP-5F8QMCQ Implementation : impl1 Synopsys Lattice Technology Mapper, Version map202003lat, Build 172R, Built Nov 2 2020 09:31:45, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 128MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 128MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 166MB peak: 166MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB) Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 172MB peak: 172MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 174MB peak: 174MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 174MB peak: 174MB) Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 174MB peak: 174MB) Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 174MB peak: 174MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:01s 1.95ns 107 / 147 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 174MB peak: 174MB) @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB) Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 138MB peak: 175MB) Writing Analyst data base C:\Users\lab\Desktop\impl1\synwork\bcd_test_impl1_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 175MB peak: 175MB) Writing EDIF Netlist and constraint files @N: FX1056 |Writing EDF file: C:\Users\lab\Desktop\impl1\bcd_test_impl1.edi @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 179MB peak: 179MB) Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 179MB peak: 180MB) @W: MT420 |Found inferred clock bin_to_bcd|CLK with period 5.00ns. Please declare a user-defined clock on port CLK. ##### START OF TIMING REPORT #####[ # Timing report written on Thu Apr 3 13:14:35 2025 # Top view: bin_to_bcd Requested Frequency: 200.0 MHz Wire load mode: top Paths requested: 3 Constraint File(s): @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 2.428 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------- bin_to_bcd|CLK 200.0 MHz 388.8 MHz 5.000 2.572 2.428 inferred Inferred_clkgroup_0 System 200.0 MHz NA 5.000 NA NA system system_clkgroup ===================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------- bin_to_bcd|CLK bin_to_bcd|CLK | 5.000 2.428 | No paths - | No paths - | No paths - ====================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: bin_to_bcd|CLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------ ready bin_to_bcd|CLK FD1P3AY Q ready 1.377 2.428 bst[32] bin_to_bcd|CLK FD1S3AX Q bst[32] 1.341 2.571 O_STB bin_to_bcd|CLK FD1P3AX Q O_STB_c 1.108 2.804 b8.DAT_1[0] bin_to_bcd|CLK FD1S3AX Q bcd8[0] 1.180 3.266 b2.DAT_1[0] bin_to_bcd|CLK FD1S3AX Q bcd2[0] 1.180 3.266 b5.DAT_1[0] bin_to_bcd|CLK FD1S3AX Q bcd5[0] 1.180 3.266 b7.DAT_1[0] bin_to_bcd|CLK FD1S3AX Q bcd7[0] 1.180 3.266 b1.DAT_1[0] bin_to_bcd|CLK FD1S3AX Q bcd1[0] 1.180 3.266 b4.DAT_1[0] bin_to_bcd|CLK FD1S3AX Q bcd4[0] 1.180 3.266 b6.DAT_1[0] bin_to_bcd|CLK FD1S3AX Q bcd6[0] 1.180 3.266 ==================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------ bst[0] bin_to_bcd|CLK FD1S3AX D I_ACK_c 4.894 2.428 O_STB bin_to_bcd|CLK FD1P3AX SP un1_O_ACK 4.528 2.571 ready bin_to_bcd|CLK FD1P3AY SP un1_I_STB 4.528 2.804 bin[0] bin_to_bcd|CLK FD1S3AX D bin_4[0] 5.089 3.095 bin[1] bin_to_bcd|CLK FD1S3AX D bin_4[1] 5.089 3.095 bin[2] bin_to_bcd|CLK FD1S3AX D bin_4[2] 5.089 3.095 bin[3] bin_to_bcd|CLK FD1S3AX D bin_4[3] 5.089 3.095 bin[4] bin_to_bcd|CLK FD1S3AX D bin_4[4] 5.089 3.095 bin[5] bin_to_bcd|CLK FD1S3AX D bin_4[5] 5.089 3.095 bin[6] bin_to_bcd|CLK FD1S3AX D bin_4[6] 5.089 3.095 ==================================================================================== Worst Path Information *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.894 - Propagation time: 2.466 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 2.428 Number of logic level(s): 1 Starting point: ready / Q Ending point: bst[0] / D The start point is clocked by bin_to_bcd|CLK [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK The end point is clocked by bin_to_bcd|CLK [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------- ready FD1P3AY Q Out 1.377 1.377 r - ready Net - - - - 65 I_ACK ORCALUT4 B In 0.000 1.377 r - I_ACK ORCALUT4 Z Out 1.089 2.466 r - I_ACK_c Net - - - - 2 bst[0] FD1S3AX D In 0.000 2.466 r - ================================================================================= Path information for path number 2: Requested Period: 5.000 - Setup time: 0.472 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.528 - Propagation time: 1.957 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 2.571 Number of logic level(s): 1 Starting point: bst[32] / Q Ending point: O_STB / SP The start point is clocked by bin_to_bcd|CLK [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK The end point is clocked by bin_to_bcd|CLK [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------- bst[32] FD1S3AX Q Out 1.341 1.341 r - bst[32] Net - - - - 42 un1_O_ACK ORCALUT4 B In 0.000 1.341 r - un1_O_ACK ORCALUT4 Z Out 0.617 1.957 r - un1_O_ACK Net - - - - 1 O_STB FD1P3AX SP In 0.000 1.957 r - ================================================================================= Path information for path number 3: Requested Period: 5.000 - Setup time: 0.472 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.528 - Propagation time: 1.725 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 2.804 Number of logic level(s): 1 Starting point: O_STB / Q Ending point: ready / SP The start point is clocked by bin_to_bcd|CLK [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK The end point is clocked by bin_to_bcd|CLK [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------- O_STB FD1P3AX Q Out 1.108 1.108 r - O_STB_c Net - - - - 3 un1_I_STB ORCALUT4 B In 0.000 1.108 r - un1_I_STB ORCALUT4 Z Out 0.617 1.725 r - un1_I_STB Net - - - - 1 ready FD1P3AY SP In 0.000 1.725 r - ================================================================================= ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 180MB peak: 180MB) Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 180MB peak: 180MB) --------------------------------------- Resource Usage Report Part: lcmxo2_4000hc-4 Register bits: 147 of 4320 (3%) PIC Latch: 0 I/O cells: 78 Details: FD1P3AX: 1 FD1P3AY: 1 FD1S3AX: 105 GSR: 1 IB: 36 INV: 1 OB: 42 OFS1P3DX: 40 ORCALUT4: 107 PUR: 1 VHI: 1 VLO: 1 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 64MB peak: 180MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Thu Apr 3 13:14:36 2025 ###########################################################]