20 Mar 13:14
r3 MI
module random3
(
input wire RST,
input wire CLK,
input wire [15:0] SEED_DAT,
input wire SEED_STB,
input wire ENABLE,
output wire [15:0] RANDOM_WORD
);
reg [15:0] r;
wire b = r[0] ^ r[14];
wire c = r[0] ^ r[13];
wire d = r[0] ^ r[11];
always @(posedge CLK or posedge RST)
if (RST) begin
r <= 1;
end else if (SEED_STB) begin
r <= SEED_DAT;
end else if (ENABLE) begin
r <= {r[0], r[15], b, c, r[12], d, r[10:1]};
end
assign RANDOM_WORD = r;
endmodule