module random123 ( input wire RST, input wire CLK, input wire [15:0] SEED_DAT, input wire SEED_STB, input wire ENABLE, output wire [15:0] RANDOM_WORD ); wire [15:0] a; wire rst = RST; wire clk = CLK; wire seed_stb = SEED_STB; random1 ran1( .RST(rst), .CLK(clk), .SEED_DAT(16'hCAFE), .SEED_STB(seed_stb), .ENABLE(1), .RANDOM_WORD(a) ); wire [15:0] b; random2 ran2( .RST(rst), .CLK(clk), .SEED_DAT(16'hCAFE), .SEED_STB(seed_stb), .ENABLE(1), .RANDOM_WORD(b) ); wire [15:0] c; random3 ran3( .RST(rst), .CLK(clk), .SEED_DAT(16'hCAFE), .SEED_STB(seed_stb), .ENABLE(1), .RANDOM_WORD(c) ); wire [15:0] sum = a + b + c; assign RANDOM_WORD = sum; endmodule