VERIBORING FINAL FINAL
//-------------------------------------------------------------------------------
// top.v
//-------------------------------------------------------------------------------
module top
(
input wire CLK_PCB,
input wire nRST_PCB,
input wire ROAD_DET,
output wire ROAD_RED,
output wire ROAD_YELLOW,
output wire ROAD_GREEN,
input wire PED_BUTT,
output wire PED_RED,
output wire PED_GREEN,
output wire [3:0] LED
);
//-------------------------------------------------------------------------------
parameter SIM = "FALSE";
//-------------------------------------------------------------------------------
wire CLK = CLK_PCB;
wire RST_PCB = ~nRST_PCB;
wire RST_async, RST_sync, RST;
//-------------------------------------------------------------------------------
assign RST_async = RST_PCB ;
//rst_synch_bridge my_rst_synch_bridge(.I_RST(RST_async), .CLK(CLK), .O_RST(RST_sync));
assign RST_sync = RST_async;
assign RST = RST_sync;
//-------------------------------------------------------------------------------
//if(SIM == "TRUE")
//-------------------------------------------------------------------------------
reg [31:0] heartbeat_clk;
//-------------------------------------------------------------------------------
always@(posedge CLK or posedge RST)
if(RST ) heartbeat_clk <= 0;
else heartbeat_clk <= heartbeat_clk + 1;
//------------------------------------------------------------------------------------------------------
assign LED = ~{ROAD_DET, PED_BUTT, RST, heartbeat_clk[27]};
//------------------------------------------------------------------------------------------------------
//assign {ROAD_RED, ROAD_YELLOW, ROAD_GREEN, PED_RED, PED_GREEN}= heartbeat_clk[26:22];
automat auto (
.RST(RST),
.CLK(CLK),
.CR(ROAD_RED),
.CY(ROAD_YELLOW),
.CG(ROAD_GREEN),
.PR(PED_RED),
.PG(PED_GREEN),
.BUZZ()
);
//------------------------------------------------------------------------------------------------------
endmodule
//-------------------------------------------------------------------------------
// automat.v
//-------------------------------------------------------------------------------
module automat #(
parameter TICK_LENGTH = 20000000 // liczba taktów na 1 sekundę
)(
input wire RST,
input wire CLK,
input wire P_P,
input wire CAR,
output wire CR,
output wire CY,
output wire CG,
output wire PR,
output wire PG,
output wire BUZZ
);
reg blinkFlag;
reg [31:0] COUNT_SEC;
reg [31:0] COUNT;
reg [2:0] NEXT_STATE;
always @(posedge CLK or posedge RST) begin
if (RST) begin
COUNT_SEC <= TICK_LENGTH;
COUNT <= 5;
NEXT_STATE <= 1;
end else begin
// sub-sekunda
if (COUNT_SEC == 0) begin
COUNT_SEC <= TICK_LENGTH;
// sekunda
if (COUNT == 0) begin
COUNT <= 6;
blinkFlag <= 0;
NEXT_STATE <= (blinkFlag) ? 1 : NEXT_STATE + 1;
end else begin
if (NEXT_STATE == 7) begin
NEXT_STATE <= 6;
blinkFlag <= 1;
end else if (NEXT_STATE == 6 & blinkFlag) begin
NEXT_STATE <= 7;
end
COUNT <= COUNT - 1;
end
end else begin
COUNT_SEC <= COUNT_SEC - 1;
end
end
end
// alias aktualnego stanu
wire [2:0] STATE = NEXT_STATE;
// mapowanie stanu na wyjścia
stan2LED s2l (
.STATE(STATE),
.CR (CR),
.CY (CY),
.CG (CG),
.PR (PR),
.PG (PG),
.BUZZ (BUZZ)
);
endmodule
//-------------------------------------------------------------------------------
// stan2LED.v
//-------------------------------------------------------------------------------
module stan2LED (
input wire [2:0] STATE,
output reg CR,
output reg CY,
output reg CG,
output reg PR,
output reg PG,
output reg BUZZ
);
always @(*) begin
// **domyślnie wyłącz wszystko**
CR = 0;
CY = 0;
CG = 0;
PR = 0;
PG = 0;
BUZZ = 0;
case (STATE)
1: begin
// czerwone auta + czerwone piesi
CR = 1;
PR = 1;
end
2: begin
// czerwone+żółte auta + czerwone piesi
CR = 1;
CY = 1;
PR = 1;
end
3: begin
// zielone auta + czerwone piesi
CG = 1;
PR = 1;
end
4: begin
// żółte auta + czerwone piesi
CY = 1;
PR = 1;
end
5: begin
// czerwone auta + czerwone piesi (powrót)
CR = 1;
PR = 1;
end
6: begin
// czerwone auta + zielone piesi
CR = 1;
PG = 1;
end
7: begin
// czerwone auta + BUZZ (piesi czekają)
CR = 1;
BUZZ = 1;
end
default: begin
// (nieużywane) jeżeli STATE=0 – wszystko off
end
endcase
end
endmodule