PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Tue May 20 11:07:08 2025 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f Mruganie_Dioda_impl1.p2t Mruganie_Dioda_impl1_map.ncd Mruganie_Dioda_impl1.dir Mruganie_Dioda_impl1.prf -gui -msgset C:/Users/lab/Documents/Mrozek FPGA/Mruganie_Dioda/promote.xml Preference file: Mruganie_Dioda_impl1.prf. Cost Table Summary Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ 5_1 * 0 - - - - 04 Completed * : Design saved. Total (real) run time for 1-seed: 4 secs par done! Note: user must run 'Trace' for timing closure signoff. Lattice Place and Route Report for Design "Mruganie_Dioda_impl1_map.ncd" Tue May 20 11:07:08 2025 Best Par Run PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset "C:/Users/lab/Documents/Mrozek FPGA/Mruganie_Dioda/promote.xml" -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 Mruganie_Dioda_impl1_map.ncd Mruganie_Dioda_impl1.dir/5_1.ncd Mruganie_Dioda_impl1.prf Preference file: Mruganie_Dioda_impl1.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file Mruganie_Dioda_impl1_map.ncd. Design name: top NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-4000HC Package: TQFP144 Performance: 4 Loading device for application par from file 'xo2c4000.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.44. Performance Hardware Data Status: Final Version 34.4. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 9+4(JTAG)/280 5% used 9+4(JTAG)/115 11% bonded IOLOGIC 5/280 1% used SLICE 51/2160 2% used GSR 1/1 100% used Number of Signals: 186 Number of Connections: 389 Pin Constraint Summary: 9 out of 9 pins locked (100% locked). The following 1 signal is selected to use the primary clock routing resources: CLK (driver: I_CLK, clk load #: 37) WARNING - par: Signal "CLK" is selected to use Primary clock resources. However, its driver comp "I_CLK" is located at "105", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. The following 1 signal is selected to use the secondary clock routing resources: state[0] (driver: SLICE_44, clk load #: 0, sr load #: 0, ce load #: 13) Signal RST_tmp is selected as Global Set/Reset. Starting Placer Phase 0. Finished Placer Phase 0. REAL time: 0 secs Starting Placer Phase 1. .................. Placer score = 12947. Finished Placer Phase 1. REAL time: 2 secs Starting Placer Phase 2. . Placer score = 12908 Finished Placer Phase 2. REAL time: 2 secs Clock Report Global Clock Resources: CLK_PIN : 0 out of 8 (0%) General PIO: 1 out of 280 (0%) PLL : 0 out of 2 (0%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Global Clocks: PRIMARY "CLK" from comp "I_CLK" on PIO site "105 (PR3A)", clk load = 37 SECONDARY "state[0]" from Q0 on comp "SLICE_44" on site "R12C15D", clk load = 0, ce load = 13, sr load = 0 PRIMARY : 1 out of 8 (12%) SECONDARY: 1 out of 8 (12%) Edge Clocks: No edge clock selected. I/O Usage Summary (final): 9 + 4(JTAG) out of 280 (4.6%) PIO sites used. 9 + 4(JTAG) out of 115 (11.3%) bonded PIO sites used. Number of PIO comps: 9; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+---------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+---------------+------------+-----------+ | 0 | 0 / 28 ( 0%) | - | - | | 1 | 1 / 29 ( 3%) | 3.3V | - | | 2 | 7 / 29 ( 24%) | 3.3V | - | | 3 | 0 / 9 ( 0%) | - | - | | 4 | 1 / 10 ( 10%) | 3.3V | - | | 5 | 0 / 10 ( 0%) | - | - | +----------+---------------+------------+-----------+ Total placer CPU time: 2 secs Dumping design to file Mruganie_Dioda_impl1.dir/5_1.ncd. ----------------------------------------------------------------- INFO - par: ASE feature is off due to non timing-driven settings. ----------------------------------------------------------------- 0 connections routed; 389 unrouted. Starting router resource preassignment Completed router resource preassignment. Real time: 3 secs Start NBR router at 11:07:11 05/20/25 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** Start NBR special constraint process at 11:07:11 05/20/25 Start NBR section for initial routing at 11:07:11 05/20/25 Level 4, iteration 1 4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 3 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) Start NBR section for normal routing at 11:07:11 05/20/25 Level 4, iteration 1 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 3 secs Level 4, iteration 2 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 3 secs Start NBR section for re-routing at 11:07:11 05/20/25 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 3 secs Start NBR section for post-routing at 11:07:11 05/20/25 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) Estimated worst slack<setup> : <n/a> Timing score<setup> : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. Total CPU time 3 secs Total REAL time: 3 secs Completely routed. End of route. 389 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 Timing score: 0 Dumping design to file Mruganie_Dioda_impl1.dir/5_1.ncd. All signals are completely routed. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack<setup/<ns>> = <n/a> PAR_SUMMARY::Timing score<setup/<ns>> = <n/a> PAR_SUMMARY::Worst slack<hold /<ns>> = <n/a> PAR_SUMMARY::Timing score<hold /<ns>> = <n/a> PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 3 secs Total REAL time to completion: 4 secs par done! Note: user must run 'Trace' for timing closure signoff. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.