#Build: Synplify Pro (R) Q-2020.03L-SP1, Build 182R, Oct 29 2020 #install: C:\lscc\diamond\3.12\synpbase #OS: Windows 8 6.2 #Hostname: DESKTOP-5F8QMCQ # Tue May 20 11:06:59 2025 #Implementation: impl1 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: DESKTOP-5F8QMCQ Implementation : impl1 Synopsys HDL Compiler, Version comp202003synp2, Build 182R, Built Oct 29 2020 10:49:53, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: DESKTOP-5F8QMCQ Implementation : impl1 Synopsys Verilog Compiler, Version comp202003synp2, Build 182R, Built Oct 29 2020 10:49:53, @ @N: : | Running in 64-bit mode @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work) @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\top.v" (library work) Verilog syntax check successful! File C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\top.v changed - recompiling Selecting top level module top @N:CG364 : machxo2.v(498) | Synthesizing module IB in library work. Running optimization stage 1 on IB ....... @N:CG364 : machxo2.v(857) | Synthesizing module OB in library work. Running optimization stage 1 on OB ....... @N:CG364 : top.v(1) | Synthesizing module top in library work. Running optimization stage 1 on top ....... @A:CL282 : top.v(50) | Feedback mux created for signal ROAD_YELLOW. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : top.v(50) | Feedback mux created for signal ROAD_RED. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : top.v(50) | Feedback mux created for signal ROAD_GREEN. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : top.v(50) | Feedback mux created for signal PED_RED. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : top.v(50) | Feedback mux created for signal PED_GREEN. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. Running optimization stage 2 on top ....... @N:CL201 : top.v(50) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 Running optimization stage 2 on OB ....... Running optimization stage 2 on IB ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== @L: C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\impl1\synwork\layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 92MB peak: 92MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue May 20 11:06:59 2025 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: DESKTOP-5F8QMCQ Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 182R, Built Oct 29 2020 10:49:53, @ @N: : | Running in 64-bit mode File C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\impl1\synwork\layer0.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 90MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue May 20 11:06:59 2025 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== @L: C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\impl1\synwork\Mruganie_Dioda_impl1_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue May 20 11:06:59 2025 ###########################################################]