Lattice Mapping Report File for Design Module 'top'



Design Information

Command line:   map -a MachXO2 -p LCMXO2-4000HC -t TQFP144 -s 4 -oc Commercial
     Mruganie_Dioda_impl1.ngd -o Mruganie_Dioda_impl1_map.ncd -pr
     Mruganie_Dioda_impl1.prf -mp Mruganie_Dioda_impl1.mrp -lpf
     C:/Users/lab/Documents/Mrozek
     FPGA/Mruganie_Dioda/impl1/Mruganie_Dioda_impl1_synplify.lpf -lpf
     C:/Users/lab/Documents/Mrozek FPGA/Mruganie_Dioda/Mruganie_Dioda.lpf -c 0
     -gui -msgset C:/Users/lab/Documents/Mrozek FPGA/Mruganie_Dioda/promote.xml
     
Target Vendor:  LATTICE
Target Device:  LCMXO2-4000HCTQFP144
Target Performance:   4
Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.0.240.2
Mapped on:  05/20/25  11:07:07


Design Summary
   Number of registers:     61 out of  4665 (1%)
      PFU registers:           56 out of  4320 (1%)
      PIO registers:            5 out of   345 (1%)
   Number of SLICEs:        51 out of  2160 (2%)
      SLICEs as Logic/ROM:     51 out of  2160 (2%)
      SLICEs as RAM:            0 out of  1620 (0%)
      SLICEs as Carry:         27 out of  2160 (1%)
   Number of LUT4s:         99 out of  4320 (2%)
      Number used as logic LUTs:         45
      Number used as distributed RAM:     0
      Number used as ripple logic:       54
      Number used as shift registers:     0
   Number of PIO sites used: 9 + 4(JTAG) out of 115 (11%)
   Number of block RAMs:  0 out of 10 (0%)
   Number of GSRs:        1 out of 1 (100%)
   EFB used :        No
   JTAG used :       No
   Readback used :   No
   Oscillator used : No
   Startup used :    No
   POR :             On
   Bandgap :         On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 6 (0%)
   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Number of PLLs:  0 out of 2 (0%)
   Number of DQSDLLs:  0 out of 2 (0%)
   Number of CLKDIVC:  0 out of 4 (0%)
   Number of ECLKSYNCA:  0 out of 4 (0%)
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  1

     Net CLK: 37 loads, 37 rising, 0 falling (Driver: PIO I_CLK )
   Number of Clock Enables:  3
     Net state[0]: 13 loads, 13 LSLICEs
     Net RST_tmp: 5 loads, 0 LSLICEs
     Net blink_counter13lt24_i: 1 loads, 1 LSLICEs
   Number of local set/reset loads for net RST_tmp merged into GSR:  56
   Number of LSRs:  0
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net counter: 33 loads
     Net blink_counter[23]: 27 loads
     Net blink_counter[24]: 27 loads
     Net blink_counter13lt23: 26 loads
     Net state[0]: 20 loads
     Net blink_flag: 6 loads
     Net RST_tmp: 6 loads
     Net counter[19]: 2 loads
     Net counter[25]: 2 loads
     Net green_flag: 2 loads




   Number of warnings:  3
   Number of errors:    0
     




Design Errors/Warnings

WARNING - map: C:/Users/lab/Documents/Mrozek
     FPGA/Mruganie_Dioda/Mruganie_Dioda.lpf(8): Semantic error in "LOCATE COMP
     "LED" SITE "20" ;": COMP "LED" cannot be found in design. This preference
     has been disabled.
WARNING - map: C:/Users/lab/Documents/Mrozek
     FPGA/Mruganie_Dioda/Mruganie_Dioda.lpf(9): Semantic error in "IOBUF PORT
     "LED" IO_TYPE=LVCMOS33 ;": Port "LED" does not exist in the design. This
     preference has been disabled.
WARNING - map: Using local reset signal 'RST_tmp' to infer global GSR net.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| O_PED_RED           | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| I_PED_DETECT        | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| I_nRST              | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| I_CLK               | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| I_ROAD_DETECT       | INPUT     | LVCMOS33  |            |

+---------------------+-----------+-----------+------------+
| O_ROAD_GREEN        | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| O_ROAD_RED          | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| O_ROAD_YELLOW       | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| O_PED_GREEN         | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+



Removed logic

Signal RST_tmp_i was merged into signal RST_tmp
Signal GND undriven or does not drive anything - clipped.
Signal counter_s_0_S1[25] undriven or does not drive anything - clipped.
Signal counter_s_0_COUT[25] undriven or does not drive anything - clipped.
Signal blink_counter_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal N_5 undriven or does not drive anything - clipped.
Signal blink_counter_cry_0_COUT[23] undriven or does not drive anything -
     clipped.
Signal counter_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal N_4 undriven or does not drive anything - clipped.
Block my_instance_ib_rst_RNISJ8E was optimized away.
Block GND_0 was optimized away.

     



GSR Usage
---------

GSR Component:
   The local reset signal 'RST_tmp' of the design has been inferred as Global
        Set Reset (GSR). The reset signal used for GSR control is 'RST_tmp'.
        

     GSR Property:
   The design components with GSR property set to ENABLED will respond to global
        set reset while the components with GSR property set to DISABLED will
        not.
        

     Components on inferred reset domain with GSR Property disabled
--------------------------------------------------------------

     These components have the GSR property set to DISABLED and are on the
     inferred reset domain. The components will respond to the reset signal
     'RST_tmp' via the local reset on the component and not the GSR component.

     Type and number of components of the type: 
   Register = 5 

     Type and instance name of component: 
   Register : PED_RED_0io
   Register : ROAD_GREEN_0io
   Register : ROAD_RED_0io

   Register : ROAD_YELLOW_0io
   Register : PED_GREEN_0io



Run Time and Memory Usage
-------------------------

   Total CPU Time: 0 secs  
   Total REAL Time: 0 secs  
   Peak Memory Usage: 49 MB
        

















































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