Synthesis Report #Build: Synplify Pro (R) Q-2020.03L-SP1, Build 182R, Oct 29 2020 #install: C:\lscc\diamond\3.12\synpbase #OS: Windows 8 6.2 #Hostname: DESKTOP-5F8QMCQ # Tue May 20 11:06:59 2025 #Implementation: impl1 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: DESKTOP-5F8QMCQ Implementation : impl1 Synopsys HDL Compiler, Version comp202003synp2, Build 182R, Built Oct 29 2020 10:49:53, @ @N|Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: DESKTOP-5F8QMCQ Implementation : impl1 Synopsys Verilog Compiler, Version comp202003synp2, Build 182R, Built Oct 29 2020 10:49:53, @ @N|Running in 64-bit mode @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work) @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\top.v" (library work) Verilog syntax check successful! File C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\top.v changed - recompiling Selecting top level module top @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":498:7:498:8|Synthesizing module IB in library work. Running optimization stage 1 on IB ....... @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":857:7:857:8|Synthesizing module OB in library work. Running optimization stage 1 on OB ....... @N: CG364 :"C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\top.v":1:7:1:9|Synthesizing module top in library work. Running optimization stage 1 on top ....... @A: CL282 :"C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\top.v":50:0:50:5|Feedback mux created for signal ROAD_YELLOW. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A: CL282 :"C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\top.v":50:0:50:5|Feedback mux created for signal ROAD_RED. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A: CL282 :"C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\top.v":50:0:50:5|Feedback mux created for signal ROAD_GREEN. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A: CL282 :"C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\top.v":50:0:50:5|Feedback mux created for signal PED_RED. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A: CL282 :"C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\top.v":50:0:50:5|Feedback mux created for signal PED_GREEN. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. Running optimization stage 2 on top ....... @N: CL201 :"C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\top.v":50:0:50:5|Trying to extract state machine for register state. Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 Running optimization stage 2 on OB ....... Running optimization stage 2 on IB ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== @L: C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\impl1\synwork\layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 92MB peak: 92MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue May 20 11:06:59 2025 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: DESKTOP-5F8QMCQ Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 182R, Built Oct 29 2020 10:49:53, @ @N|Running in 64-bit mode File C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\impl1\synwork\layer0.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 90MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue May 20 11:06:59 2025 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== @L: C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\impl1\synwork\Mruganie_Dioda_impl1_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue May 20 11:06:59 2025 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: DESKTOP-5F8QMCQ Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 182R, Built Oct 29 2020 10:49:53, @ @N|Running in 64-bit mode File C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\impl1\synwork\Mruganie_Dioda_impl1_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 90MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue May 20 11:07:01 2025 ###########################################################] # Tue May 20 11:07:01 2025 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: DESKTOP-5F8QMCQ Implementation : impl1 Synopsys Lattice Technology Pre-mapping, Version map202003lat, Build 172R, Built Nov 2 2020 09:31:45, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @A: MF827 |No constraint file specified. @L: C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\impl1\Mruganie_Dioda_impl1_scck.rpt See clock summary report "C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\impl1\Mruganie_Dioda_impl1_scck.rpt" @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 128MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 128MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB) Encoding state machine state[2:0] (in view: work.top(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB) Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB) @N: FX1184 |Applying syn_allowed_resources blockrams=10 on top level netlist top Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------- 0 - top|I_CLK 100.0 MHz 10.000 inferred Inferred_clkgroup_0 61 ============================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example --------------------------------------------------------------------------------------------------- top|I_CLK 61 I_CLK(port) green_flag.C - my_instance_ib_clk.I(IB) =================================================================================================== @W: MT529 :"c:\users\lab\documents\mrozek fpga\mruganie_dioda\top.v":50:0:50:5|Found inferred clock top|I_CLK which controls 61 sequential elements including state[1]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 61 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks ============================== Non-Gated/Non-Generated Clocks ============================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance -------------------------------------------------------------------------------------------- @KP:ckid0_0 my_instance_ib_clk.O IB 61 state[1] ============================================================================================ ##### END OF CLOCK OPTIMIZATION REPORT ###### @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 170MB peak: 170MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 170MB peak: 171MB) Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 87MB peak: 172MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue May 20 11:07:02 2025 ###########################################################] # Tue May 20 11:07:02 2025 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03L-SP1 Install: C:\lscc\diamond\3.12\synpbase OS: Windows 6.2 Hostname: DESKTOP-5F8QMCQ Implementation : impl1 Synopsys Lattice Technology Mapper, Version map202003lat, Build 172R, Built Nov 2 2020 09:31:45, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 128MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 128MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 166MB peak: 166MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB) @N: MO231 :"c:\users\lab\documents\mrozek fpga\mruganie_dioda\top.v":50:0:50:5|Found counter in view:work.top(verilog) instance blink_counter[24:0] @N: MO231 :"c:\users\lab\documents\mrozek fpga\mruganie_dioda\top.v":50:0:50:5|Found counter in view:work.top(verilog) instance counter[25:0] Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB) Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB) Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:01s 4.33ns 47 / 61 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB) @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 174MB peak: 174MB) Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 138MB peak: 174MB) Writing Analyst data base C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\impl1\synwork\Mruganie_Dioda_impl1_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 174MB peak: 174MB) Writing EDIF Netlist and constraint files @N: FX1056 |Writing EDF file: C:\Users\lab\Documents\Mrozek FPGA\Mruganie_Dioda\impl1\Mruganie_Dioda_impl1.edi @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 179MB peak: 179MB) Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 179MB peak: 179MB) @W: MT420 |Found inferred clock top|I_CLK with period 10.00ns. Please declare a user-defined clock on port I_CLK. ##### START OF TIMING REPORT #####[ # Timing report written on Tue May 20 11:07:05 2025 # Top view: top Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 3.470 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------- top|I_CLK 100.0 MHz 153.1 MHz 10.000 6.530 3.470 inferred Inferred_clkgroup_0 ===================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------ top|I_CLK top|I_CLK | 10.000 3.470 | No paths - | No paths - | No paths - ============================================================================================================ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: top|I_CLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------- blink_counter[0] top|I_CLK FD1P3DX Q blink_counter[0] 1.044 3.470 blink_counter[1] top|I_CLK FD1P3DX Q blink_counter[1] 1.044 3.470 blink_counter[2] top|I_CLK FD1P3DX Q blink_counter[2] 1.044 3.470 blink_counter[6] top|I_CLK FD1P3DX Q blink_counter[6] 1.044 3.470 blink_counter[7] top|I_CLK FD1P3DX Q blink_counter[7] 1.044 3.470 state[1] top|I_CLK FD1S3DX Q counter 1.321 3.766 blink_counter[3] top|I_CLK FD1P3DX Q blink_counter[3] 1.044 4.050 blink_counter[4] top|I_CLK FD1P3DX Q blink_counter[4] 1.044 4.050 counter[0] top|I_CLK FD1S3DX Q counter[0] 0.972 4.115 blink_counter[5] top|I_CLK FD1P3DX Q blink_counter[5] 1.044 4.192 ============================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------- blink_flag top|I_CLK FD1P3DX SP blink_counter13lt24_i 9.528 3.470 blink_counter[23] top|I_CLK FD1P3DX D blink_counter_lm[23] 10.089 3.764 blink_counter[24] top|I_CLK FD1P3DX D blink_counter_lm[24] 10.089 3.764 counter[25] top|I_CLK FD1S3DX D counter_s[25] 9.894 3.766 blink_counter[21] top|I_CLK FD1P3DX D blink_counter_lm[21] 10.089 3.907 blink_counter[22] top|I_CLK FD1P3DX D blink_counter_lm[22] 10.089 3.907 counter[23] top|I_CLK FD1S3DX D counter_s[23] 9.894 3.909 counter[24] top|I_CLK FD1S3DX D counter_s[24] 9.894 3.909 blink_counter[0] top|I_CLK FD1P3DX D blink_counter_lm[0] 10.089 4.031 blink_counter[1] top|I_CLK FD1P3DX D blink_counter_lm[1] 10.089 4.031 ==================================================================================================== Worst Path Information *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.472 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.528 - Propagation time: 6.058 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 3.470 Number of logic level(s): 5 Starting point: blink_counter[0] / Q Ending point: blink_flag / SP The start point is clocked by top|I_CLK [rising] (rise=0.000 fall=5.000 period=10.000) on pin CK The end point is clocked by top|I_CLK [rising] (rise=0.000 fall=5.000 period=10.000) on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------ blink_counter[0] FD1P3DX Q Out 1.044 1.044 r - blink_counter[0] Net - - - - 2 blink_counter13lto5_1_0 ORCALUT4 A In 0.000 1.044 r - blink_counter13lto5_1_0 ORCALUT4 Z Out 1.017 2.061 f - blink_counter13lto5_1_0 Net - - - - 1 blink_counter13lto5 ORCALUT4 A In 0.000 2.061 f - blink_counter13lto5 ORCALUT4 Z Out 1.017 3.077 f - blink_counter13lt10 Net - - - - 1 blink_counter13lto15 ORCALUT4 A In 0.000 3.077 f - blink_counter13lto15 ORCALUT4 Z Out 1.017 4.094 f - blink_counter13lt16 Net - - - - 1 blink_counter13lto22 ORCALUT4 A In 0.000 4.094 f - blink_counter13lto22 ORCALUT4 Z Out 1.347 5.441 f - blink_counter13lt23 Net - - - - 26 blink_flag_RNO ORCALUT4 A In 0.000 5.441 f - blink_flag_RNO ORCALUT4 Z Out 0.617 6.058 r - blink_counter13lt24_i Net - - - - 1 blink_flag FD1P3DX SP In 0.000 6.058 r - ========================================================================================== ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 179MB peak: 179MB) Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 179MB peak: 179MB) --------------------------------------- Resource Usage Report Part: lcmxo2_4000hc-4 Register bits: 61 of 4320 (1%) PIC Latch: 0 I/O cells: 9 Details: CCU2D: 27 FD1P3DX: 26 FD1S3DX: 30 GSR: 1 IB: 4 INV: 1 OB: 5 OFS1P3DX: 5 ORCALUT4: 45 PUR: 1 VHI: 1 VLO: 1 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 63MB peak: 179MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Tue May 20 11:07:06 2025 ###########################################################]