Place & Route TRACE Report
Loading design for application trce from file mruganie_dioda_impl1.ncd.
Design name: top
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-4000HC
Package: TQFP144
Performance: 4
Loading device for application trce from file 'xo2c4000.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Tue May 20 11:07:12 2025
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Mruganie_Dioda_impl1.twr -gui -msgset C:/Users/lab/Documents/Mrozek FPGA/Mruganie_Dioda/promote.xml Mruganie_Dioda_impl1.ncd Mruganie_Dioda_impl1.prf
Design file: mruganie_dioda_impl1.ncd
Preference file: mruganie_dioda_impl1.prf
Device,speed: LCMXO2-4000HC,4
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "CLK" 269.469000 MHz (1292 errors)
1741 items scored, 1292 timing errors detected.
Warning: 116.401MHz is the maximum frequency for this preference.
Report Type: based on TRACE automatically generated preferences
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY NET "CLK" 269.469000 MHz ;
1741 items scored, 1292 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 4.880ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q blink_counter[11] (from CLK +)
Destination: FF Data in blink_counter[24] (to CLK +)
Delay: 8.425ns (28.9% logic, 71.1% route), 5 logic levels.
Constraint Details:
8.425ns physical path delay SLICE_32 to SLICE_39 exceeds
3.711ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 3.545ns) by 4.880ns
Physical Path Details:
Data path SLICE_32 to SLICE_39:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R14C16C.CLK to R14C16C.Q1 SLICE_32 (from CLK)
ROUTE 2 1.420 R14C16C.Q1 to R12C15D.A1 blink_counter[11]
CTOF_DEL --- 0.495 R12C15D.A1 to R12C15D.F1 SLICE_44
ROUTE 1 1.535 R12C15D.F1 to R16C15D.B0 blink_counter13lto14_2
CTOF_DEL --- 0.495 R16C15D.B0 to R16C15D.F0 SLICE_46
ROUTE 1 0.315 R16C15D.F0 to R16C16A.D1 blink_counter13lt16
CTOF_DEL --- 0.495 R16C16A.D1 to R16C16A.F1 SLICE_45
ROUTE 26 2.723 R16C16A.F1 to R15C18B.B0 blink_counter13lt23
CTOF_DEL --- 0.495 R15C18B.B0 to R15C18B.F0 SLICE_39
ROUTE 1 0.000 R15C18B.F0 to R15C18B.DI0 blink_counter_lm[24] (to CLK)
--------
8.425 (28.9% logic, 71.1% route), 5 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R14C16C.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_39:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R15C18B.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 4.871ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q blink_counter[1] (from CLK +)
Destination: FF Data in blink_counter[24] (to CLK +)
Delay: 8.416ns (34.8% logic, 65.2% route), 6 logic levels.
Constraint Details:
8.416ns physical path delay SLICE_27 to SLICE_39 exceeds
3.711ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 3.545ns) by 4.871ns
Physical Path Details:
Data path SLICE_27 to SLICE_39:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R16C15B.CLK to R16C15B.Q1 SLICE_27 (from CLK)
ROUTE 2 1.011 R16C15B.Q1 to R16C15A.B1 blink_counter[1]
CTOF_DEL --- 0.495 R16C15A.B1 to R16C15A.F1 SLICE_43
ROUTE 1 1.004 R16C15A.F1 to R16C15D.B1 blink_counter13lto5_1_0
CTOF_DEL --- 0.495 R16C15D.B1 to R16C15D.F1 SLICE_46
ROUTE 1 0.436 R16C15D.F1 to R16C15D.C0 blink_counter13lt10
CTOF_DEL --- 0.495 R16C15D.C0 to R16C15D.F0 SLICE_46
ROUTE 1 0.315 R16C15D.F0 to R16C16A.D1 blink_counter13lt16
CTOF_DEL --- 0.495 R16C16A.D1 to R16C16A.F1 SLICE_45
ROUTE 26 2.723 R16C16A.F1 to R15C18B.B0 blink_counter13lt23
CTOF_DEL --- 0.495 R15C18B.B0 to R15C18B.F0 SLICE_39
ROUTE 1 0.000 R15C18B.F0 to R15C18B.DI0 blink_counter_lm[24] (to CLK)
--------
8.416 (34.8% logic, 65.2% route), 6 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R16C15B.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_39:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R15C18B.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 4.834ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q blink_counter[0] (from CLK +)
Destination: FF Data in blink_counter[24] (to CLK +)
Delay: 8.379ns (34.9% logic, 65.1% route), 6 logic levels.
Constraint Details:
8.379ns physical path delay SLICE_27 to SLICE_39 exceeds
3.711ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 3.545ns) by 4.834ns
Physical Path Details:
Data path SLICE_27 to SLICE_39:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R16C15B.CLK to R16C15B.Q0 SLICE_27 (from CLK)
ROUTE 2 0.974 R16C15B.Q0 to R16C15A.A1 blink_counter[0]
CTOF_DEL --- 0.495 R16C15A.A1 to R16C15A.F1 SLICE_43
ROUTE 1 1.004 R16C15A.F1 to R16C15D.B1 blink_counter13lto5_1_0
CTOF_DEL --- 0.495 R16C15D.B1 to R16C15D.F1 SLICE_46
ROUTE 1 0.436 R16C15D.F1 to R16C15D.C0 blink_counter13lt10
CTOF_DEL --- 0.495 R16C15D.C0 to R16C15D.F0 SLICE_46
ROUTE 1 0.315 R16C15D.F0 to R16C16A.D1 blink_counter13lt16
CTOF_DEL --- 0.495 R16C16A.D1 to R16C16A.F1 SLICE_45
ROUTE 26 2.723 R16C16A.F1 to R15C18B.B0 blink_counter13lt23
CTOF_DEL --- 0.495 R15C18B.B0 to R15C18B.F0 SLICE_39
ROUTE 1 0.000 R15C18B.F0 to R15C18B.DI0 blink_counter_lm[24] (to CLK)
--------
8.379 (34.9% logic, 65.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R16C15B.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_39:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R15C18B.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 4.803ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q blink_counter[14] (from CLK +)
Destination: FF Data in blink_counter[24] (to CLK +)
Delay: 8.348ns (29.1% logic, 70.9% route), 5 logic levels.
Constraint Details:
8.348ns physical path delay SLICE_34 to SLICE_39 exceeds
3.711ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 3.545ns) by 4.803ns
Physical Path Details:
Data path SLICE_34 to SLICE_39:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R14C16D.CLK to R14C16D.Q0 SLICE_34 (from CLK)
ROUTE 2 1.343 R14C16D.Q0 to R12C15D.B1 blink_counter[14]
CTOF_DEL --- 0.495 R12C15D.B1 to R12C15D.F1 SLICE_44
ROUTE 1 1.535 R12C15D.F1 to R16C15D.B0 blink_counter13lto14_2
CTOF_DEL --- 0.495 R16C15D.B0 to R16C15D.F0 SLICE_46
ROUTE 1 0.315 R16C15D.F0 to R16C16A.D1 blink_counter13lt16
CTOF_DEL --- 0.495 R16C16A.D1 to R16C16A.F1 SLICE_45
ROUTE 26 2.723 R16C16A.F1 to R15C18B.B0 blink_counter13lt23
CTOF_DEL --- 0.495 R15C18B.B0 to R15C18B.F0 SLICE_39
ROUTE 1 0.000 R15C18B.F0 to R15C18B.DI0 blink_counter_lm[24] (to CLK)
--------
8.348 (29.1% logic, 70.9% route), 5 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_34:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R14C16D.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_39:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R15C18B.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 4.794ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q blink_counter[6] (from CLK +)
Destination: FF Data in blink_counter[24] (to CLK +)
Delay: 8.339ns (35.1% logic, 64.9% route), 6 logic levels.
Constraint Details:
8.339ns physical path delay SLICE_30 to SLICE_39 exceeds
3.711ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 3.545ns) by 4.794ns
Physical Path Details:
Data path SLICE_30 to SLICE_39:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R16C16C.CLK to R16C16C.Q0 SLICE_30 (from CLK)
ROUTE 2 0.974 R16C16C.Q0 to R16C16D.A1 blink_counter[6]
CTOF_DEL --- 0.495 R16C16D.A1 to R16C16D.F1 SLICE_47
ROUTE 1 0.436 R16C16D.F1 to R16C16D.C0 blink_counter13lto10_1
CTOF_DEL --- 0.495 R16C16D.C0 to R16C16D.F0 SLICE_47
ROUTE 1 0.964 R16C16D.F0 to R16C15D.A0 blink_counter13lto10_3
CTOF_DEL --- 0.495 R16C15D.A0 to R16C15D.F0 SLICE_46
ROUTE 1 0.315 R16C15D.F0 to R16C16A.D1 blink_counter13lt16
CTOF_DEL --- 0.495 R16C16A.D1 to R16C16A.F1 SLICE_45
ROUTE 26 2.723 R16C16A.F1 to R15C18B.B0 blink_counter13lt23
CTOF_DEL --- 0.495 R15C18B.B0 to R15C18B.F0 SLICE_39
ROUTE 1 0.000 R15C18B.F0 to R15C18B.DI0 blink_counter_lm[24] (to CLK)
--------
8.339 (35.1% logic, 64.9% route), 6 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_30:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R16C16C.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_39:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R15C18B.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 4.660ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q blink_counter[12] (from CLK +)
Destination: FF Data in blink_counter[24] (to CLK +)
Delay: 8.205ns (29.6% logic, 70.4% route), 5 logic levels.
Constraint Details:
8.205ns physical path delay SLICE_33 to SLICE_39 exceeds
3.711ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 3.545ns) by 4.660ns
Physical Path Details:
Data path SLICE_33 to SLICE_39:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R14C16A.CLK to R14C16A.Q0 SLICE_33 (from CLK)
ROUTE 2 1.200 R14C16A.Q0 to R12C15D.C1 blink_counter[12]
CTOF_DEL --- 0.495 R12C15D.C1 to R12C15D.F1 SLICE_44
ROUTE 1 1.535 R12C15D.F1 to R16C15D.B0 blink_counter13lto14_2
CTOF_DEL --- 0.495 R16C15D.B0 to R16C15D.F0 SLICE_46
ROUTE 1 0.315 R16C15D.F0 to R16C16A.D1 blink_counter13lt16
CTOF_DEL --- 0.495 R16C16A.D1 to R16C16A.F1 SLICE_45
ROUTE 26 2.723 R16C16A.F1 to R15C18B.B0 blink_counter13lt23
CTOF_DEL --- 0.495 R15C18B.B0 to R15C18B.F0 SLICE_39
ROUTE 1 0.000 R15C18B.F0 to R15C18B.DI0 blink_counter_lm[24] (to CLK)
--------
8.205 (29.6% logic, 70.4% route), 5 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_33:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R14C16A.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_39:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R15C18B.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 4.633ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q blink_counter[2] (from CLK +)
Destination: FF Data in blink_counter[24] (to CLK +)
Delay: 8.178ns (35.8% logic, 64.2% route), 6 logic levels.
Constraint Details:
8.178ns physical path delay SLICE_28 to SLICE_39 exceeds
3.711ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 3.545ns) by 4.633ns
Physical Path Details:
Data path SLICE_28 to SLICE_39:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R14C15A.CLK to R14C15A.Q0 SLICE_28 (from CLK)
ROUTE 2 0.773 R14C15A.Q0 to R16C15A.C1 blink_counter[2]
CTOF_DEL --- 0.495 R16C15A.C1 to R16C15A.F1 SLICE_43
ROUTE 1 1.004 R16C15A.F1 to R16C15D.B1 blink_counter13lto5_1_0
CTOF_DEL --- 0.495 R16C15D.B1 to R16C15D.F1 SLICE_46
ROUTE 1 0.436 R16C15D.F1 to R16C15D.C0 blink_counter13lt10
CTOF_DEL --- 0.495 R16C15D.C0 to R16C15D.F0 SLICE_46
ROUTE 1 0.315 R16C15D.F0 to R16C16A.D1 blink_counter13lt16
CTOF_DEL --- 0.495 R16C16A.D1 to R16C16A.F1 SLICE_45
ROUTE 26 2.723 R16C16A.F1 to R15C18B.B0 blink_counter13lt23
CTOF_DEL --- 0.495 R15C18B.B0 to R15C18B.F0 SLICE_39
ROUTE 1 0.000 R15C18B.F0 to R15C18B.DI0 blink_counter_lm[24] (to CLK)
--------
8.178 (35.8% logic, 64.2% route), 6 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_28:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R14C15A.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_39:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R15C18B.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 4.519ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q blink_counter[11] (from CLK +)
Destination: FF Data in blink_flag (to CLK +)
Delay: 7.948ns (30.6% logic, 69.4% route), 5 logic levels.
Constraint Details:
7.948ns physical path delay SLICE_32 to SLICE_40 exceeds
3.711ns delay constraint less
0.000ns skew and
0.282ns CE_SET requirement (totaling 3.429ns) by 4.519ns
Physical Path Details:
Data path SLICE_32 to SLICE_40:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R14C16C.CLK to R14C16C.Q1 SLICE_32 (from CLK)
ROUTE 2 1.420 R14C16C.Q1 to R12C15D.A1 blink_counter[11]
CTOF_DEL --- 0.495 R12C15D.A1 to R12C15D.F1 SLICE_44
ROUTE 1 1.535 R12C15D.F1 to R16C15D.B0 blink_counter13lto14_2
CTOF_DEL --- 0.495 R16C15D.B0 to R16C15D.F0 SLICE_46
ROUTE 1 0.315 R16C15D.F0 to R16C16A.D1 blink_counter13lt16
CTOF_DEL --- 0.495 R16C16A.D1 to R16C16A.F1 SLICE_45
ROUTE 26 0.750 R16C16A.F1 to R16C16A.B0 blink_counter13lt23
CTOF_DEL --- 0.495 R16C16A.B0 to R16C16A.F0 SLICE_45
ROUTE 1 1.496 R16C16A.F0 to R17C15C.CE blink_counter13lt24_i (to CLK)
--------
7.948 (30.6% logic, 69.4% route), 5 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R14C16C.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_40:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R17C15C.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 4.510ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q blink_counter[1] (from CLK +)
Destination: FF Data in blink_flag (to CLK +)
Delay: 7.939ns (36.9% logic, 63.1% route), 6 logic levels.
Constraint Details:
7.939ns physical path delay SLICE_27 to SLICE_40 exceeds
3.711ns delay constraint less
0.000ns skew and
0.282ns CE_SET requirement (totaling 3.429ns) by 4.510ns
Physical Path Details:
Data path SLICE_27 to SLICE_40:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R16C15B.CLK to R16C15B.Q1 SLICE_27 (from CLK)
ROUTE 2 1.011 R16C15B.Q1 to R16C15A.B1 blink_counter[1]
CTOF_DEL --- 0.495 R16C15A.B1 to R16C15A.F1 SLICE_43
ROUTE 1 1.004 R16C15A.F1 to R16C15D.B1 blink_counter13lto5_1_0
CTOF_DEL --- 0.495 R16C15D.B1 to R16C15D.F1 SLICE_46
ROUTE 1 0.436 R16C15D.F1 to R16C15D.C0 blink_counter13lt10
CTOF_DEL --- 0.495 R16C15D.C0 to R16C15D.F0 SLICE_46
ROUTE 1 0.315 R16C15D.F0 to R16C16A.D1 blink_counter13lt16
CTOF_DEL --- 0.495 R16C16A.D1 to R16C16A.F1 SLICE_45
ROUTE 26 0.750 R16C16A.F1 to R16C16A.B0 blink_counter13lt23
CTOF_DEL --- 0.495 R16C16A.B0 to R16C16A.F0 SLICE_45
ROUTE 1 1.496 R16C16A.F0 to R17C15C.CE blink_counter13lt24_i (to CLK)
--------
7.939 (36.9% logic, 63.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R16C15B.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_40:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R17C15C.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 4.473ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q blink_counter[0] (from CLK +)
Destination: FF Data in blink_flag (to CLK +)
Delay: 7.902ns (37.0% logic, 63.0% route), 6 logic levels.
Constraint Details:
7.902ns physical path delay SLICE_27 to SLICE_40 exceeds
3.711ns delay constraint less
0.000ns skew and
0.282ns CE_SET requirement (totaling 3.429ns) by 4.473ns
Physical Path Details:
Data path SLICE_27 to SLICE_40:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R16C15B.CLK to R16C15B.Q0 SLICE_27 (from CLK)
ROUTE 2 0.974 R16C15B.Q0 to R16C15A.A1 blink_counter[0]
CTOF_DEL --- 0.495 R16C15A.A1 to R16C15A.F1 SLICE_43
ROUTE 1 1.004 R16C15A.F1 to R16C15D.B1 blink_counter13lto5_1_0
CTOF_DEL --- 0.495 R16C15D.B1 to R16C15D.F1 SLICE_46
ROUTE 1 0.436 R16C15D.F1 to R16C15D.C0 blink_counter13lt10
CTOF_DEL --- 0.495 R16C15D.C0 to R16C15D.F0 SLICE_46
ROUTE 1 0.315 R16C15D.F0 to R16C16A.D1 blink_counter13lt16
CTOF_DEL --- 0.495 R16C16A.D1 to R16C16A.F1 SLICE_45
ROUTE 26 0.750 R16C16A.F1 to R16C16A.B0 blink_counter13lt23
CTOF_DEL --- 0.495 R16C16A.B0 to R16C16A.F0 SLICE_45
ROUTE 1 1.496 R16C16A.F0 to R17C15C.CE blink_counter13lt24_i (to CLK)
--------
7.902 (37.0% logic, 63.0% route), 6 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R16C15B.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_40:
Name Fanout Delay (ns) Site Resource
ROUTE 37 3.055 105.PADDI to R17C15C.CLK CLK
--------
3.055 (0.0% logic, 100.0% route), 0 logic levels.
Warning: 116.401MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "CLK" 269.469000 MHz ; | 269.469 MHz| 116.401 MHz| 5 *
| | |
----------------------------------------------------------------------------
1 preference(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
blink_counter13lt23 | 26| 580| 44.89%
| | |
blink_counter13lt16 | 1| 416| 32.20%
| | |
counter | 33| 301| 23.30%
| | |
counter_cry[12] | 1| 271| 20.98%
| | |
counter_cry[10] | 1| 266| 20.59%
| | |
counter_cry[14] | 1| 262| 20.28%
| | |
counter_cry[8] | 1| 249| 19.27%
| | |
counter_cry[16] | 1| 230| 17.80%
| | |
counter_cry[6] | 1| 222| 17.18%
| | |
counter_cry[18] | 1| 199| 15.40%
| | |
counter_cry[4] | 1| 181| 14.01%
| | |
blink_counter_cry[12] | 1| 156| 12.07%
| | |
blink_counter13lt10 | 1| 156| 12.07%
| | |
blink_counter_cry[10] | 1| 154| 11.92%
| | |
counter_cry[20] | 1| 150| 11.61%
| | |
blink_counter_cry[14] | 1| 150| 11.61%
| | |
blink_counter_cry[8] | 1| 144| 11.15%
| | |
blink_counter_cry[16] | 1| 136| 10.53%
| | |
blink_counter13lto10_3 | 1| 130| 10.06%
| | |
blink_counter13lto22_3 | 1| 130| 10.06%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 1 clocks:
Clock Domain: CLK Source: I_CLK.PAD Loads: 37
Covered under: FREQUENCY NET "CLK" 269.469000 MHz ;
Timing summary (Setup):
---------------
Timing errors: 1292 Score: 2253299
Cumulative negative slack: 2253299
Constraints cover 1741 paths, 1 nets, and 375 connections (96.40% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
Tue May 20 11:07:12 2025
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Mruganie_Dioda_impl1.twr -gui -msgset C:/Users/lab/Documents/Mrozek FPGA/Mruganie_Dioda/promote.xml Mruganie_Dioda_impl1.ncd Mruganie_Dioda_impl1.prf
Design file: mruganie_dioda_impl1.ncd
Preference file: mruganie_dioda_impl1.prf
Device,speed: LCMXO2-4000HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "CLK" 269.469000 MHz (0 errors) 1741 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "CLK" 269.469000 MHz ;
1741 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q counter[0] (from CLK +)
Destination: FF Data in counter[0] (to CLK +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_0 to SLICE_0 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_0 to SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R17C12A.CLK to R17C12A.Q1 SLICE_0 (from CLK)
ROUTE 1 0.130 R17C12A.Q1 to R17C12A.A1 counter[0]
CTOF_DEL --- 0.101 R17C12A.A1 to R17C12A.F1 SLICE_0
ROUTE 1 0.000 R17C12A.F1 to R17C12A.DI1 counter_s[0] (to CLK)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C12A.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C12A.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q counter[24] (from CLK +)
Destination: FF Data in counter[24] (to CLK +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_15 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_15 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R17C15A.CLK to R17C15A.Q1 SLICE_15 (from CLK)
ROUTE 1 0.130 R17C15A.Q1 to R17C15A.A1 counter[24]
CTOF_DEL --- 0.101 R17C15A.A1 to R17C15A.F1 SLICE_15
ROUTE 1 0.000 R17C15A.F1 to R17C15A.DI1 counter_s[24] (to CLK)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C15A.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C15A.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q counter[23] (from CLK +)
Destination: FF Data in counter[23] (to CLK +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_15 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_15 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R17C15A.CLK to R17C15A.Q0 SLICE_15 (from CLK)
ROUTE 1 0.130 R17C15A.Q0 to R17C15A.A0 counter[23]
CTOF_DEL --- 0.101 R17C15A.A0 to R17C15A.F0 SLICE_15
ROUTE 1 0.000 R17C15A.F0 to R17C15A.DI0 counter_s[23] (to CLK)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C15A.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C15A.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q counter[21] (from CLK +)
Destination: FF Data in counter[21] (to CLK +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_16 to SLICE_16 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_16 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R17C14D.CLK to R17C14D.Q0 SLICE_16 (from CLK)
ROUTE 1 0.130 R17C14D.Q0 to R17C14D.A0 counter[21]
CTOF_DEL --- 0.101 R17C14D.A0 to R17C14D.F0 SLICE_16
ROUTE 1 0.000 R17C14D.F0 to R17C14D.DI0 counter_s[21] (to CLK)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C14D.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C14D.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q counter[22] (from CLK +)
Destination: FF Data in counter[22] (to CLK +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_16 to SLICE_16 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_16 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R17C14D.CLK to R17C14D.Q1 SLICE_16 (from CLK)
ROUTE 1 0.130 R17C14D.Q1 to R17C14D.A1 counter[22]
CTOF_DEL --- 0.101 R17C14D.A1 to R17C14D.F1 SLICE_16
ROUTE 1 0.000 R17C14D.F1 to R17C14D.DI1 counter_s[22] (to CLK)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C14D.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C14D.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q counter[20] (from CLK +)
Destination: FF Data in counter[20] (to CLK +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_17 to SLICE_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_17 to SLICE_17:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R17C14C.CLK to R17C14C.Q1 SLICE_17 (from CLK)
ROUTE 1 0.130 R17C14C.Q1 to R17C14C.A1 counter[20]
CTOF_DEL --- 0.101 R17C14C.A1 to R17C14C.F1 SLICE_17
ROUTE 1 0.000 R17C14C.F1 to R17C14C.DI1 counter_s[20] (to CLK)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C14C.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C14C.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q counter[17] (from CLK +)
Destination: FF Data in counter[17] (to CLK +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_18 to SLICE_18 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_18 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R17C14B.CLK to R17C14B.Q0 SLICE_18 (from CLK)
ROUTE 1 0.130 R17C14B.Q0 to R17C14B.A0 counter[17]
CTOF_DEL --- 0.101 R17C14B.A0 to R17C14B.F0 SLICE_18
ROUTE 1 0.000 R17C14B.F0 to R17C14B.DI0 counter_s[17] (to CLK)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C14B.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C14B.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q counter[18] (from CLK +)
Destination: FF Data in counter[18] (to CLK +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_18 to SLICE_18 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_18 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R17C14B.CLK to R17C14B.Q1 SLICE_18 (from CLK)
ROUTE 1 0.130 R17C14B.Q1 to R17C14B.A1 counter[18]
CTOF_DEL --- 0.101 R17C14B.A1 to R17C14B.F1 SLICE_18
ROUTE 1 0.000 R17C14B.F1 to R17C14B.DI1 counter_s[18] (to CLK)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C14B.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C14B.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q counter[16] (from CLK +)
Destination: FF Data in counter[16] (to CLK +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_19 to SLICE_19 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_19 to SLICE_19:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R17C14A.CLK to R17C14A.Q1 SLICE_19 (from CLK)
ROUTE 1 0.130 R17C14A.Q1 to R17C14A.A1 counter[16]
CTOF_DEL --- 0.101 R17C14A.A1 to R17C14A.F1 SLICE_19
ROUTE 1 0.000 R17C14A.F1 to R17C14A.DI1 counter_s[16] (to CLK)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C14A.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C14A.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q counter[15] (from CLK +)
Destination: FF Data in counter[15] (to CLK +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay SLICE_19 to SLICE_19 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path SLICE_19 to SLICE_19:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R17C14A.CLK to R17C14A.Q0 SLICE_19 (from CLK)
ROUTE 1 0.130 R17C14A.Q0 to R17C14A.A0 counter[15]
CTOF_DEL --- 0.101 R17C14A.A0 to R17C14A.F0 SLICE_19
ROUTE 1 0.000 R17C14A.F0 to R17C14A.DI0 counter_s[15] (to CLK)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path I_CLK to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C14A.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path I_CLK to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 37 1.120 105.PADDI to R17C14A.CLK CLK
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "CLK" 269.469000 MHz ; | 0.000 ns| 0.377 ns| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 1 clocks:
Clock Domain: CLK Source: I_CLK.PAD Loads: 37
Covered under: FREQUENCY NET "CLK" 269.469000 MHz ;
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1741 paths, 1 nets, and 375 connections (96.40% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 1292 (setup), 0 (hold)
Score: 2253299 (setup), 0 (hold)
Cumulative negative slack: 2253299 (2253299+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------