22 May 12:35
fianl
module mytestbenchmodule();
reg CLK;
initial CLK = 0;
always #5 CLK = ~CLK; // Zegar co 10 ns
reg RST;
initial begin
RST = 1;
#20 RST = 0;
end
integer fi, fo;
integer count;
reg error;
integer f1, f2, f3, f4;
reg [31:0] vec_Are, vec_Aim, vec_Bre, vec_Bim;
reg [31:0] expected_Cre, expected_Cim;
// sygnaly handshake
reg I_STB;
wire I_ACK;
wire O_STB;
reg O_ACK;
wire [31:0] Cre, Cim;
initial begin
fi = $fopen("input.txt", "r");
fo = $fopen("output.txt", "r");
I_STB = 0;
O_ACK = 0;
error = 0;
@(negedge RST);
forever begin
count = $fscanf(fi, "%d %d %d %d\n", f1, f2, f3, f4);
if (count != 4) begin
$display("Koniec pliku wejsciowego.");
$finish;
end
vec_Are = f1;
vec_Aim = f2;
vec_Bre = f3;
vec_Bim = f4;
// Podaj dane do complex_mul
@(posedge CLK);
I_STB = 1;
wait (I_ACK);
@(posedge CLK);
I_STB = 0;
// Czekaj na dane wyjsciowe
wait (O_STB);
@(posedge CLK);
O_ACK = 1;
@(posedge CLK);
O_ACK = 0;
// Odczytaj oczekiwany wynik
count = $fscanf(fo, "%d %d\n", expected_Cre, expected_Cim);
if (count != 2) begin
$display("Koniec pliku wyjsciowego.");
$finish;
end
if ((Cre !== expected_Cre) || (Cim !== expected_Cim)) begin
$display("BLAD: Cre=%d (oczekiwano %d), Cim=%d (oczekiwano %d)", Cre, expected_Cre, Cim, expected_Cim);
error = error + 1;
end else begin
$display("OK: Cre=%d, Cim=%d", Cre, Cim);
end
@(posedge CLK);
end
end
// instancja complex_mul
complex_mul cmul (
.CLK(CLK),
.RST(RST),
.I_STB(I_STB),
.I_ACK(I_ACK),
.I_ARE(vec_Are),
.I_AIM(vec_Aim),
.I_BRE(vec_Bre),
.I_BIM(vec_Bim),
.O_STB(O_STB),
.O_ACK(O_ACK),
.O_CRE(Cre),
.O_CIM(Cim)
);
endmodule