10 Apr 12:01
module mytestbenchmodule();
reg CLK;
initial CLK <= 0;
always #50 CLK <= ~CLK;
reg RST;
initial
begin
RST <= 0;
RST <= #100 1;
RST <= #500 0;
end
reg [15:0] i_dat_a;
reg [15:0] i_dat_b;
reg i_stb;
reg o_ack;
initial
begin
o_ack <= 0;
i_stb <= 0;
#1051;
i_dat_a <= 15;
i_dat_b <= 22;
i_stb <= 1;
#100;
i_stb <= 0;
#4000;
o_ack <= 1;
end
adder
#(
.A_WIDTH(16),
.B_WIDTH(16)
)
adder1
(
.CLK(CLK),
.RST(RST),
.I_DAT_A(i_dat_a),
.I_DAT_B(i_dat_b),
.I_STB(i_stb),
.I_ACK(),
.O_DAT(),
.O_STB(),
.O_ACK(o_ack)
);
endmodule module adder
#(
parameter A_WIDTH = 32,
parameter B_WIDTH = 32
)
(
input wire RST,
input wire CLK,
input wire I_STB,
output wire I_ACK,
input wire [A_WIDTH-1:0] I_DAT_A,
input wire [B_WIDTH-1:0] I_DAT_B,
output reg O_STB,
output reg [(A_WIDTH>B_WIDTH?A_WIDTH:B_WIDTH) : 0] O_DAT,
input wire O_ACK
);
assign I_ACK = I_STB & ~O_STB;
always @(posedge CLK or posedge RST)
if (RST) O_DAT <= 0; else if (I_ACK) O_DAT <= I_DAT_A+I_DAT_B;
always @(posedge CLK or posedge RST)
if (RST) O_STB <= 0; else if (O_ACK) O_STB <= 0; else if (I_ACK) O_STB <= 1;
endmodule